1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including substitutable redundant cells.
2. Description of the Background Art
An example of a conventional semiconductor memory device including redundant cells will be briefly described with reference to FIG. 32.
A conventional semiconductor memory device 9000 shown in FIG. 32 includes a register 901, a row address buffer 902, a row predecoder 212, a redundancy determining circuit 211, a memory cell array 910, a column decoder 903 and a data input/output buffer 904. The conventional semiconductor memory device 9000 has a configuration implementing hierarchical word lines and shared sense amplifier.
Memory cell array 910 includes a plurality of memory blocks 1.0, 1, 1 . . . , . Each memory block includes a normal block (in the figure, represented by the reference characters NBL (0), NBL (1), . . . ) constituted by normal memory cells, and a redundant block (in the figure, represented by the reference characters RBL (0), RBL (1), . . . ) constituted by redundant cells. On both sides of each of memory blocks 1.0, . . . , sense amplifier blocks 2 are arranged. Adjacent memory blocks share one sense amplifier block 2.
Register 901 receives external signals (external row address strobe signal /RAS, external column address strobe signal /CAS, external chip selected signal /CS, chip select signal /CS, external write enable signal /WE, external clock signal CLK, external clock enable signal /CKE and so on), and provides corresponding control signals.
Row address buffer 902 provides a row address signal in response to external address signals (A0 to Ai). Row predecoder 212 provides a decode signal designating a main word line MWL based on an output from row address buffer 902, in response to an enable signal PDE output from redundancy determining circuit 211. Row predecoder 212 further provides, based on an output from row address buffer 902, a corresponding block selecting signal.
Data input/output buffer 904 is for signal exchange between data I/O pins DQ0 to DQn and memory cell array 910 under the control of column decoder 903.
An SD driver/SA driver 924 and an MWL driver 925 are provided for memory cell array 910. SD driver /SA driver 924 provides a shared gate signal for controlling activation of the sense amplifier, and a subdecode signal for activating a word line. MWL driver 925 sets a main word line to a selected state.
Redundancy determining circuit 211 determines whether redundancy is to be used or not. When redundancy is to be used, a redundant main word line selecting signal for setting a redundant main word line RMWL to the selected state, is provided.
An WL driver 914 shown in FIG. 33 is arranged for each of the memory blocks 1.0, . . . .
Configuration of WL driver 914 in the conventional semiconductor memory device shown in FIG. 32 will be described with reference to FIG. 33.
Memory block 1.1 includes a plurality of redundant and normal memory cells MC, a plurality of bit line pairs BL (0) and /BL (0), . . . , a plurality of word lines WL (n), WL (n+1), . . . . , and a plurality of spare word lines SWL (0), SWL (1), . . . . The plurality of bit line pairs are arranged corresponding to respective columns. The plurality of word lines and the spare word lines are arranged corresponding to respective rows.
Sense amplifier blocks (2a, 2b in the figure) are arranged for memory block 1.1. Sense amplifier blocks 2a and 2b each include a plurality of sense amplifiers S/A, a plurality of equalize circuits constituted by PMOS transistors PT10 and a plurality of S/A share circuits constituted by NMOS transistors NT10, NT11, NT12 and NT13.
WL driver 914 sets one of word lines WL(n) and WL(n+1) or one of spare word lines SWL(0) and SWL(1) to the selected state, based on signals on main word lines MWL(0), . . . , MWL(m) or the signal on redundant main word line RMWL and based on subdecode signals SD(0), /SD(0), SD(1), /SD(1), . . . . The redundant main word line and the spare word lines are used for selecting a redundant cell.
WL driver 914 includes, corresponding to each word line and spare word line, PMOS transistor PT1 and NMOS transistors NT1 and NT2. For example, PMOS transistor PT1 provided for word line WL(0) has one terminal receiving subdecode signal SD(1) and the other terminal connected to one terminal of NMOS transistor NT1. PMOS transistor PT1 and NMOS transistor NT1 have respective gate electrodes connected to main word line MWL. A connection node between PMOS transistor PT1 and NMOS transistor NT1 is connected to word line WL(0). NMOS transistor NT2 has one terminal connected to word line WL(0), the other terminal connected to the ground potential, and receives at its gate electrode, a subdecode signal /SD (1) which is an inversion of subdecode signal SD(1). As a result, by the subdecode signal or the redundant subdecode signal, any one of the word lines or the spare word lines is set to the selected state.
A memory cell array having redundancy area arrangement has come to be indispensable in a semiconductor memory device. The conventional semiconductor memory device 9000 shown in FIG. 32 is, in this point, provided with a structure having high repairing efficiency, as substitution over memory blocks is possible.
Generally, however, in the semiconductor memory device including redundant cells, a block to be activated is not determined until after redundancy determination, and therefore access speed is not satisfactorily high.
This problem will be described with reference to FIGS. 34A to 34M, taking the conventional semiconductor memory device shown in FIG. 32 as a specific example.
Referring to FIGS. 34A to 34M, by a bank activation signal ACT, operation of row system starts. Address signals RA0 to RA12 are latched, a word line or a spare word line is selected, and sense amplifiers are activated. When a word line is selected, whether redundancy is to be used or not is determined.
At time t0, the row address reaches redundancy determining circuit 211 and row predecoder 212. Redundancy determination takes place in the period .tau.0. After redundancy determination, at time t1, a subdecode signal or a redundant subdecode signal is activated to set the corresponding word line or the spare word line to the selected state, and sense amplifiers are set ready.
More specifically, when memory block 1.1 is selected, sense amplifier blocks positioned at opposing ends thereof are set to the active state. In preparation for the operation, in order to cancel equalized state of the bit lines, equalize signal BLEQ is set to the L level, and in order to turn off the shared gate, shared gates SHR (U) and SHE (D) are set to the L level. These operations are completed after redundancy determination and before the rise of the word line.
As a result, a time period of .tau.0+.tau.20 (where .tau.20=t2-t0) is necessary, from the input of the row address to the rise of the word line.
Another problem is that the layout area is increased when redundant cells are provided.